1. Field of the Invention
The present disclosure generally relates to the field of semiconductor manufacturing, and, more particularly, to contact elements and vias formed in a dielectric material system on the basis of high aspect ratio openings.
2. Description of the Related Art
Semiconductor devices, such as advanced integrated circuits, typically contain a very high number of circuit elements, such as transistors, capacitors, resistors and the like, which are usually formed in a substantially planar configuration above an appropriate substrate having formed thereon a semiconductor layer. Due to the high number of circuit elements and the required complex layout of modern integrated circuits, the electrical connections of the individual circuit elements may generally not be established within the same level on which the circuit elements are manufactured, but require a plurality of additional wiring layers, which are also referred to as metallization layers. These metallization layers generally include metal-containing lines, providing the inner-level electrical connection, and also include a plurality of inter-level connections, which are also referred to as vias, that are filled with an appropriate metal and provide the electrical connection between two neighboring stacked metallization layers.
Due to the continuous reduction of the feature sizes of circuit elements in modern integrated circuits, the number of circuit elements for a given chip area, that is, the packing density of the circuit elements, also increases, thereby necessitating an adequate number of electrical connections to provide the desired circuit functionality. Therefore, the number of stacked metallization layers usually increases as the number of circuit elements per chip area becomes larger, while, nevertheless, the sizes of individual metal lines and vias are reduced.
Similarly, the contact structure of the semiconductor device, which may be considered as an interface connecting the circuit elements of the device level with the metallization system, has to be adapted to the reduced feature sizes in the device level and the metallization system. For this reason, very sophisticated patterning strategies may have to be applied in order to provide the contact elements with the required density and with appropriate reduced dimensions, at least at the device level side, in order to connect to the contact regions, such as drain and source regions, gate electrode structures and the like, without contributing to pronounced leakage current paths and even short circuits and the like. In many conventional approaches, the contact elements or contact plugs are typically formed by using a tungsten-based metal together with an interlayer dielectric stack that is typically comprised of silicon dioxide in combination with an etch stop material, such as a silicon nitride material. Due to the very reduced critical dimensions of the circuit elements, such as the transistors, the respective contact elements have to be formed on the basis of contact openings with an aspect ratio which may be as high as approximately 8:1 or more, wherein a diameter of the contact openings may be 0.1 μm or significantly less for transistor devices of, for instance, the 65 nm technology node. In even further sophisticated approaches, and in very densely packed device regions, the width of the contact openings may be 50 nm and less. Generally, an aspect ratio of such contact openings may be defined as the ratio of the depth of the opening relative to the width of the opening.
Hence, after providing the contact opening with the required minimum width, an appropriate conductive material, such as tungsten, possibly in combination with an appropriate barrier layer system, has to be deposited, which may typically be accomplished on the basis of a sputter deposition technique, for instance, for the barrier materials, and chemical vapor deposition (CVD)-like process recipes for forming the tungsten material.
Upon further reducing the critical dimensions of transistor elements, the complexity of the patterning process, i.e., of the lithography process and the subsequent etch process for forming the openings in the interlayer dielectric material system, may result in severe contact failures when densely packed device regions are considered. For example, in densely packed device regions, transistors and, thus, gate electrode structures have to be positioned close to each other in view of the corresponding design requirements, wherein drain and source regions may have to be contacted between the closely spaced gate electrode structures, however, without producing leakage paths to the gate electrode. Consequently, the patterning process has to provide contact openings with a lateral width that is less than the spacing between closely spaced gate electrode structures, while at the same time a high degree of accuracy in appropriately aligning the corresponding etch mask may result in extremely reduced process margins.
In sophisticated semiconductor devices, the lateral distance between closely spaced gate electrode structures may require a minimum lateral dimension of the contact openings that may be well beyond the capabilities of the lithography process, thereby requiring appropriate etch strategies in order to reduce the critical dimensions, at least at the bottom of the contact openings, in an appropriate manner that enables the contacting of critical drain and source areas without unduly increasing the probability of creating leakage paths or short circuits between the contact elements and the gate electrode structures.
With reference to FIGS. 1a-1d, a typical approach for forming sophisticated contact elements will now be described in more detail.
FIG. 1a schematically illustrates a cross-sectional view of a semiconductor device 100 in an advanced manufacturing stage, in which contact elements are to be formed so as to connect to critical device areas in a semiconductor material. As shown, the semiconductor device 100 comprises a substrate 101, above which is provided a semiconductor layer 102, such as a silicon layer, which, in turn, may comprise a plurality of active regions 102A, i.e., semiconductor regions, in and above which transistor elements are formed. For convenience, a single active region 102A is illustrated in FIG. 1a and may represent a semiconductor region, above which a plurality of gate electrode structures 110 are formed. For example, the gate electrode structures 110 represent closely spaced gate electrode structures 110A, 110B, 110C, which have critical dimensions of 50 nm and less, while also a spacing between the individual gate electrode structures 110 may be of the same order of magnitude. For example, the gate electrode structures 110 may comprise an electrode material 111 that is separated from the active region 102A by a gate dielectric material 112. Furthermore, frequently the gate electrode structures 110 may comprise a spacer structure 113, for instance in the form of an oxide material, a nitride material and the like. It should be appreciated, however, that, in this manufacturing stage, the spacer structure 113 may have been removed, if considered appropriate for the further processing of the device 100. Between the closely spaced gate electrode structures 110, corresponding contact regions 102C may be provided, at least some of which may have to be contacted by corresponding contact elements 125A, 125B, indicated as dashed lines, which have to be formed during the further processing of the device 100. Consequently, the contact element 125A, 125B may have lateral design dimensions, which are less than the lateral distance at least between the gate electrode materials 111, wherein also a certain process tolerance in view of any misalignments during the further processing may have to be taken into consideration. The contact elements 125A, 125B have to be formed in an interlayer dielectric material system 120, which may be comprised of any appropriate material, such as silicon dioxide, silicon nitride and the like. In the example shown, the material system 120 may comprise substantially a single material 121, which may provide the desired gap fill capabilities upon depositing the dielectric material, thereby reliably filling the space between the closely spaced gate electrode structures 110.
The semiconductor device 100 may be formed on the basis of the following processes. Appropriate active regions in the semiconductor layer 102 are formed by using well-established process techniques for incorporating an isolation structure (not shown) which laterally delineates the corresponding active regions 102A. Thereafter, materials for the gate electrode structures 110 and for the patterning thereof are deposited or formed by any other process techniques, followed by complex lithography and etch strategies in order to provide the gate electrode structures 110 with the desired lateral dimensions and the lateral distance according to the design rules of the device 100. It should be appreciated that, in some sophisticated approaches, the gate electrode structures 110 may be formed on the basis of a high-k dielectric material in combination with a metal-containing electrode material, while, in other cases, any such sophisticated material systems may be provided in a further advanced manufacturing stage, for instance prior to completing the dielectric material system 120, and the like. Thereafter, any further processes may be performed, such as incorporating any required materials into the semiconductor layer 102, for instance with respect to adjusting the strain conditions and the like, followed by the incorporation of appropriate dopant species, as is required for forming drain and source regions of transistors, a part of which may be represented by the gate electrode structures 110. During these manufacturing processes, also the spacer structure 113 or at least a portion thereof may be provided in accordance with the overall process and device requirements. After any anneal processes, the conductivity of the contact regions 102C may be increased, for instance, by forming a metal silicide and the like, while, in other cases, any such processes may be applied after patterning the dielectric material system 120. The one or more materials of the system 120 may be provided on the basis of well-established deposition techniques, wherein, in sophisticated applications, process parameters and materials of the system 120 are selected such that a reliable filling of the space between the closely spaced gate electrode structures 110 is accomplished. To this end, in some cases, an appropriate etch stop layer (not shown) may be provided, while, in other cases, a substantially homogeneous material composition is formed, for instance on the basis of a silicon dioxide material, wherein the resulting surface topography, caused by the gate electrode structures 110, is typically planarized by performing appropriate processes, such as chemical mechanical polishing (CMP) and the like. Thereafter, any further deposition processes are performed in order to provide an appropriate material system for performing sophisticated lithography and etch processes in order to pattern the material 120 for forming appropriate contact openings for the contact element 125A, 125B. To this end, a planarization material, which may typically be provided in the form of a polymer material, is provided, for instance by spin-on techniques and the like, followed by the deposition of an appropriate anti-reflective coating (ARC) layer. Finally, at least one resist layer is formed above the material system whose thickness and material composition is selected so as to comply with the requirements of a sophisticated exposure process for defining the lateral size and position of contact openings to be formed in the material system 120.
FIG. 1b schematically illustrates a cross-sectional view of the semiconductor device 100 in a further advanced manufacturing stage. As shown, a stack of material layers 130 is formed above the dielectric material system 120 and comprises a resist layer 131, followed by an ARC layer 132 and a planarization layer 133. This layer system is patterned on the basis of sophisticated lithography techniques, in which the resist material 131 is exposed on the basis of a lithography mask in order to form latent images in the resist material 131, which may result, after developing the resist material, in corresponding mask openings 131A that coarsely define the lateral size and position of contact openings 121A to be formed in the material system 120. It should be appreciated that the openings 131A are typically formed with process margins of the corresponding lithography process that may be at or near the limits of the resolution capability of the lithography process. Based on the openings 131A, the ARC layer 132 is typically patterned by using an appropriate etch strategy, wherein frequently the process parameters of the etch process are selected so as to form the corresponding openings 132A in the ARC material with a pronounced degree of tapering, which is to be understood as providing sidewall surface areas 132S with a desired grade sidewall angle, indicated as angle α.
It should be appreciated that a sidewall angle of any etched openings is hereinafter to be understood as the average angle formed by the sidewall surface areas with respect to a surface normal. Thus, a substantially perpendicular surface corresponds to a sidewall angle of zero. Consequently, the openings 132A may have a reduced lateral dimension, at least at the bottom thereof, and may thus act as an efficient etch mask for the patterning of the planarization layer 133 in order to form openings 133A therein. Thus, the openings 133A may typically have a reduced lateral width compared to the mask openings 131A initially formed in the resist material 131. On the basis of the mask openings 133A, the material 120 is patterned by using any well-established anisotropic etch strategies, wherein, typically, also a certain degree of tapering is desirable in order to further reduce the lateral dimensions of the contact openings 121A, at least in the vicinity of the gate electrode structures 110.
It is well known that plasma-assisted anisotropic etch recipes rely on process parameters, such as plasma power, reactive components, polymer residues and the like, which may affect the finally-achieved vertical and lateral etch rate. For example, upon increasing directionality and kinetic energy of ions that are present in the etch ambient, a more pronounced reduction of the lateral etch rate may be achieved. Furthermore, adding specific polymerizing gas components may also provide an efficient mechanism for controlling the lateral etch rate, since any such polymerizing gas components may result in a more or less pronounced generation of etch byproducts which may preferably accumulate at the sidewalls 121S within the openings 121A. It should be appreciated, however, that generally the degree of controllability of the lateral etch rate may also significantly depend on the material composition of the basic material to be etched so that, generally, a very limited range for modulating the lateral dimensions of the contact openings 121A during a corresponding etch process is available. For example, silicon dioxide, which is a well-established dielectric material for passivating critical circuit elements, such as the gate electrode structures 110, may allow only a very moderate degree of tapering during the plasma-assisted etch process so that at least the mask opening 133A has to be appropriately adapted with respect to the design rules of the gate electrode structures 110 in order to form the contact openings 121A while reducing the probability of exposing any electrode material 111 during the corresponding etch process.
It should be appreciated that, prior to or during the entire patterning strategy for patterning the layer system 130 and the dielectric material system 120, at least a portion of the materials of the system 130 may be removed, if considered appropriate. At least after exposing the contact regions 102C, any sacrificial material may be removed and the processing is continued by filling the contact openings 121A with a conducting material, such as tungsten, and the like, possibly in combination with appropriate barrier materials, if required.
FIG. 1c schematically illustrates the semiconductor device 100 in a further advanced manufacturing stage. As illustrated, the contact elements 125A, 125B comprise an appropriate conductive material 126 and thus provide an electrical connection to the contact regions 102C. For sophisticated applications, in which the lateral distance between the gate electrode structures 110 has to be reduced in view of the corresponding design rules, in particular at areas 114, a certain risk exists that leakage paths or short circuits may be generated between the contact elements 125A, 125B and some of the gate electrode structures 110.
FIG. 1d schematically illustrates the situation for the semiconductor device 100 when even further sophisticated design rule requirements have to be implemented. As shown, the lateral distance between the gate electrode structures 110 may have to be reduced, wherein the dashed line schematically illustrates the lateral size of a corresponding contact element 125, which may be formed on the basis of the process strategy as described above with reference to FIGS. 1a-1c. In this case, the above-described process sequence will nearly certainly result in the exposure of the electrode material 111 of at least some of the gate electrode structures 110, thereby creating severe contact failures. Consequently, for highly sophisticated applications requiring design dimensions of approximately 40 nm and less for the gate electrode structures 110, the above-specified process strategy may be less than desirable in device areas comprising closely-spaced gate electrode structures. For this reason, in some conventional approaches, it has been suggested to form a dielectric liner material after patterning the contact openings in order to cover any exposed critical areas, such as exposed portions of the electrode material 111. To this end, additional deposition steps are required and a subsequent patterning process may have to be performed in order to reliably reopen the contact openings at the bottom thereof, wherein, however, still a reliable coverage of critical areas within the contact openings is to be preserved. Hence, a very limited shrinkage of contact openings may be achieved on the basis of the additional liner material, while, at the same time, the overall process complexity, for instance with respect to deposition and patterning processes, is increased.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.